Integrated circuit scaling hits roadblocks when approaching atomic level feature sizes. One solution is the use of nanotechnologies to decrease the device dimensions to few atoms levels. Another solution is scaling in the orthogonal direction to the conventional device plane - the 3D integration. Although nanotechnologies and 3D integration appears to be competing for the solution to the same problem, a deeper analysis shows that they actually complement each other. This talk will explore current and future research area where a combination of 3D and nanotechnologies provides system level solutions that can not be afforded otherwise.