İbrahim Çinar, Aisha Gokce Ozbay, Özgür Burak Aslan, Onur Dinçer and Vedat Karakaş
This project is supported by EU Marie Curie IRG Grant PCM-256281 and Bogazici University Research Fund 12B03M1
Electrical Characterization of Phase Change Memory Switching Conditions and Long Term Drift of Reset Resistance
In order to characterize the switching parameters of phase change memory devices in the time domain as a function of substrate temperature we have built a computer controlled electrical network consisting of a semiconductor device analyzer and a nanosecond pulser connected via a bias tee. The dc and ac grounds were separated using floating ground of the semiconductor device analyzer. The PCM devices to be tested were mounted on a gold-coated vacuum chuck with a variable temperature setting and electrically contacted with RF probes. The stability of the contacts was assured by performing the measurements on a vibration isolation table and the contact quality was constantly monitored with an optical microscope zoomed onto the contact electrodes. The current that flowed through the device during switching and the device resistance was probed using a 6GHz bandwidth oscilloscope connected to a ~1kohm surface mount resistor in series with and in close proximity to the device under test with a constant 20mV (non-destructive) read bias as shown below.
Switching between set and reset states was successfully demonstrated with this setup for device dimensions from 10 µm to 50 nm and previously observed dependence of the reset current on device geometry was reproduced. A representative switching data for a 500 nm diameter circular device is shown below. Such measurements were also repeated at elevated temperatures and a corresponding decrease in threshold reset current values was observed as expected.
Pulsed reset operation for a 500 nm diameter PCM device
PCM devices with various top contact sizes with circular, square or rectangular geometries have been tested. Devices have a range of resistance values from SET levels of 200 Ω – 5 kΩ to RESET levels of 200 kΩ – 10 MΩ. We have consistently observed an intermediate resistance level for a range of programming voltages in square top-contact devices with resistance levels 10 kΩ – 120 kΩ whereas in circular devices we have not seen such a state.
Current-Voltage (IV) characteristics are observed for the complete range of resistances. Figure 2 shows a typical IV sweep initiated when the device is at a RESET state, for a 130 nm square top contact device. The amorphous phase resistance of 3 MΩ switches to 350 Ω , crystalline phase, above the threshold voltage of 800 mV. We have observed that the threshold voltage is not constant and varies (from 350 mV- 1V for this sample) depending on the initial state of system. The sourcemeter is set to a current protection level of 1 mA to protect the device, therefore the IV curves show the compliance value rather than the actual current. Measurements conducted on square top contact geometry devices show a two-step switching behavior as illustrated in Figure 3 which plots the IV curve for a 0.5 µm square top contact device. The resistance first drops to middle state value before changing to set state.
Pulsed-resistance measurements are conducted to determine a programming range for the devices. A voltage pulse is sent to the device which is at a set state and an IV curve up to 100 mV is obtained right after the pulse to determine the resistance level. The device is then set again for the application of the next voltage pulse. The figure below shows the pulsed-resistance measurements comparing circular (a) and square (b) top-contact geometry devices. The circular top contact device displays a sudden change in resistance (from 1.5 kΩ to 900 kΩ) for pulse amplitudes higher than 0.65 V. Such a behavior is representative of circular top contact devices of 60-75 nm diameters that have a range of resistance values from 1 – 8 kΩ for set state and 800 kΩ – 3 MΩ for reset state. We consistently observe a multi-level switching for increasing voltage pulse amplitudes for square as well as rectangular top contact PCM cells. The example shown in Figure 4b is representative of a 90 nm square top contact device which displays a resistance increase from a set state of 700 Ω to a 24 kΩ resistance state, an intermediate resistance state, around 1.2 V and a second switching is observed around 1.45 V to a reset state with a resistance of 197 kΩ. It is clear that the 24 kΩ resistance state is a stable intermediate resistance state since there is a range of programming voltages between 1.25-1.4 V. As will be discussed later, circular top contact geometry devices favor a homogeneous current distribution around the edges of the top contact inside the GST layer whereas the square top contact geometry devices cause current crowding at the corners of the top contact hence allow a heterogeneous current distribution which causes regions with mixed-phase inside the active region for certain voltage pulses.
To elaborate the stability of the three resistance states: reset, set or middle state; we have monitored the time evolution of the resistance of the device under test after a switching operation. We have developed several Labview programming virtual instruments called VIs to perform different types of drift measurements such as drift under constant DC bias with a sourcemeter, or under constant DC bias with a battery (see next section), drift after discrete time intervals (like 5 minutes) recorded as IV curves for long periods of time (up to a day).
Programming of Reset and Intermediate States
Pulsed-Resistance measurements for (a) 75 nm circular top contact device, (b) 90 nm square top contact device. Resistance of the device is measured after the application of a 50 ns width pulse with 2 ns trailing edge for the given amplitude to the set state.
Drift of Resistance Levels
The drift in resistance levels of a reset state is common in PCM devices and is attributed to structural relaxation through annihilation of charge traps which play a major role in the conduction of electrons. The resistance change is indicative of a power-law behavior characterized by a drift coefficient.
Resistance drift data for set (blue diamonds), middle (black circles) and reset (red triangles). The initial resistance levels at t0=100sec are 428Ω, 114kΩ and 1MΩ, respectively. The drift coefficients are 0.0009 for set, 0.0102 for middle and 0.102 for reset states.
We have obtained resistance drift data for set and middle states as well. For set state, there is almost no drift as illustrated above. The device plotted in this figure is a 130 nm square device and it is set via an IV measurement to a resistance level of 428.84Ω. The resistance change is less than 2Ω in a 12 hour period. The drift coefficient of the particular device is 0.0009 and varies between 0.0006-0.001 this value for other samples. Figure 10 shows the resistance drift data for the same sample when it is switched to the middle state by the application of a 1.8 V pulse with 100 ns width and 2 ns trailing edge. Even though this state has much higher resistance than the set state, 116 kΩ, the drift is only slightly different than the set state. The drift coefficient is 0.0102, much smaller than the drift coefficient of the reset state. The υ for middle state varies within the range 0.01-0.015 for other samples.
Drift at Nano-Millisecond Time Scales
The resistance switching of a PCM cell from a set state to a reset state has been captured using a 25ps resolution LeCroy Oscilloscope. An illustration of the circuit design is shown below where the oscilloscope is connected parallel to the device. In order to overcome ground-loop currents and additional noise sources, the source-meter used in pulsed-resistance measurements is replaced with a DC circuit box consisting of two 12 V batteries and a series of ballast resistors to adjust the current running through the device. The ballast resistors and the internal resistance of the oscilloscope are adjusted so that the oscilloscope reads a reasonable change in voltage when the phase of the PCM cell changes from crystalline to amorphous. The best results are obtained when the oscilloscope settings are adjusted to DC coupling to a 1MΩ internal resistance.
Nano-Millisecond Drift Measurement Setup
The resistance drift behaviour for a 130 nm square device after a 100 ns 2V pulse.
Temperature Dependence of Resistance Drift
Temperature dependence of the drift coefficient for a 500 nm square device is obtained for the middle resistance state. The device was switched to middle state with a 2.8 V pulse with 100 ns width and 2 ns trailing edge. For all other devices we have observed that the drift coefficient increases with increasing temperature up until 100 C after which the re-crystallization effect kick in and reduces the device resistance.
Post Switching Pulse Treatment
Post-reset treatments have been examined with the aim to reduce the resistance drift. First, resistance drift data for the particular sample is recorded after a reset operation and the device is set back to crystalline state. Then a reset pulse and a post-reset pulse are sourced to the device and the time evolution of the resistance is observed. Post-reset treatment for a 500 nm square top contact sample is shown in Figure 8. A reset pulse of 2.5V is used to switch this device and a post-reset pulse of 1.8 V is sent to the device right after the switching pulse. The reset resistance appears to have increased slightly after the post-reset treatment, however the drift coefficients are very similar: 0.107 for the reset measurement and 0.108 for the measurement after the post-reset pulse. We have tried post-reset pulses from 1.5 V up to 2.8 V and seen that the drift coefficient remains almost the same.
Finite Element Simulations of Phase Change Memory Devices
To get a detailed description of the temperature and phase distribution in the experimental conditions a finite element code has been implemented using COMSOL multiphysics and critical switching properties such as a large contrast in the resistance states were successfully reproduced. These simulations will help us understand the role of inhomogeneous heating in different contact geometries for long term drift behaviour. We have already gained invaluable insights into the phase change kinetics during switching as shown below. For instance such simulations guide us on how to get stable, reproducible multi-level switching behaviour.